//input signal READYX shouldn't be set to 0 until it is processed.
module strict_priority(
    input CLK, RST_N,
    input READY0, READY1, READY2, READY3, 
    input READY4, READY5, READY6, READY7,
    output reg [7:0] READY_OUT // one-hot ,0000_0000 represents arbiter not working
);

always@(posedge CLK or negedge RST_N)begin
    if(!RST_N)
        READY_OUT = 8'd0;
    else if(READY0)
        READY_OUT = 8'd1;
    else if(READY1)
        READY_OUT = 8'd2;
    else if(READY2)
        READY_OUT = 8'd4;
    else if(READY3)
        READY_OUT = 8'd8;
    else if(READY4)
        READY_OUT = 8'd16;
    else if(READY5)
        READY_OUT = 8'd32;
    else if(READY6)
        READY_OUT = 8'd64;
    else if(READY7)
        READY_OUT = 8'd128;
    else 
        READY_OUT = 8'd0;
end

endmodule
